The present invention relates to a circuit for converting data inputted thereto in parallel and outputting serial data.
Although needs for a high-speed semiconductor memory device are gradually increasing, there are physical limitations on an access time of a core region, i.e., a memory cell array region, in the semiconductor memory device. Therefore, the semiconductor memory device internally processes data in parallel and uses a scheme of serializing the data and inputting/outputting serialized data in a high speed when inputting/outputting the data, thereby overcoming the physical limitations of the core region. For the purpose, a parallel to serial conversion circuit is used to convert the data internally processed in parallel to serial data and output the serial data to the outside of the semiconductor memory device.
FIG. 1 illustrates a conventional parallel to serial conversion circuit.
Referring to FIG. 1, the parallel to serial conversion circuit includes a driver constructed of a multiplexer 110 and inverters 121 and 122.
Continuous data are transferred to a first line DATA1 and a second line DATA2 and the multiplexer 110 sequentially selects the data on the first line DATA1 and the data on the second line DATA2, and outputs the selected data in response to a clock CLK. In a period where the clock CLK has a high level, the multiplexer 110 outputs the data on the first line DATA1 to an output node A. On the other hand, in a period where the clock CLK has a low level, the multiplexer 110 outputs the data on the second line DATA2 to the output node A.
FIG. 2 is a timing diagram showing an operation of the conventional parallel to serial conversion circuit described in FIG. 1.
As illustrated in FIG. 2, data D0, D2, D4 and D6 are continuously and sequentially inputted to the first line DATA1 and data D1, D3, D5 and D7 are continuously and sequentially inputted to the second line DATA2. The multiplexer 110 selects the data on the first line DATA1 and outputs the selected data through its output node A in the period where the clock CLK has the high level. On the other hand, the multiplexer 110 selects the data on the second line DATA2 and outputs the selected data through its output node A in the period where the clock CLK has the low level. Therefore, the data on the first and second lines DATA1 and DATA2 are serially arranged and outputted through the output node A in order of D0, D1, D2, D3, D4, D5, D6 and D7.
The parallel data on the first and second lines DATA1 and DATA2 are serially outputted to the output node A of the parallel to serial conversion circuit. Accordingly, the data on the output node A swing in a speed twice larger than that of the data on the first and second lines DATA1 and DATA2. However, in this condition, as a speed of a system employing the parallel to serial conversion circuit increases, the data on the output node A may not swing fully. Thus, there occur problems relating to inter-symbol interference (ISI) such as the increase of a jitter component.
Furthermore, since the multiplexer 110 changes the parallel data to the serial data, there exists the node A where the data inputted through the different lines DATA1 and DATA2 are commonly produced. Since large capacitance is generated at the node A, a swing width of the data on the node A is further limited. As a result, a problem that data having a high frequency cannot swing as it should and thus the data disappear may be generated.